Electronic apparatus and method of conserving energy

ABSTRACT

An electronic apparatus and a method of conserving energy comprises providing an energy-conservation module to control use of one or more energy-saving mechanism by a hardware element. The energy-conservation module comprises a performance estimation module that estimates a performance level requirement of the hardware element and a slack time. A cost-benefit qualifier module is provided that uses one or more generic algorithm and at least one separate record that characterizes power use and performance by the hardware element in relation to a Performance Power state of the selected energy-saving mechanism in order to determine an existence of an energy saving. The cost-benefit qualifier module sets the hardware element to use the Performance Power state of the selected energy-saving mechanism if the energy-saving exists.

FIELD OF THE INVENTION

This invention relates to an electronic apparatus of the type, forexample, that comprises a replenishable power source, such as a batteryor fuel cell. The present invention also relates to a method ofconserving energy of the type, for example, supplied by a replenishablepower source, such as a battery or a fuel cell.

BACKGROUND OF THE INVENTION

In the field of portable electronic devices, it is known to enablefreedom from tethering to a mains power source by providing a portableelectronic device with a capability to use batteries or fuel cells,either disposable or rechargeable.

Consequently, an important consideration in relation to the portabledevice is power consumption as this impacts upon how quickly the energyof the battery is depleted and hence the amount of time for which theportable device can be used.

Despite gradual improvements in recent decades, battery technology hasnot kept pace with power consumption demands of the latest portableelectronic devices, like handheld computing devices and third generation(3G) mobile phones. Hardware designers are therefore using advancedpower—saving mechanisms to help minimise Integrated Circuit (IC) andsystem power consumption.

In this respect, new generations of applications processors, basebandprocessors, power management ICs and other platform components nowinclude the advanced power management hardware mechanisms, for exampleDynamic Frequency Scaling (DFS), Dynamic Voltage Scaling (DVS), andmultiple idle modes such as so-called “Wait”, “Deep Sleep” and/or“Hibernate” modes. Power reduction and energy conservation is achievedby placing hardware blocks into lower power states, where performance isalso lower or non-existent. To do this dynamically while programs arerunning requires an accurate knowledge of ever-changing workload thatsoftware being executed requires of various blocks of hardware making upthe portable device, for example a processor and/or peripherals.Therefore, most of the above mechanisms do not yield significant energyconservation, and thus better battery life, unless intelligent softwareis used to exploit effectively the power-saving techniques built intothe hardware.

Energy-Conserving Software (ECS) uses predictive and/or a prioritechniques to determine the varying run-time workload needed by theprocessor (or processors) and other Power-Managed Components (PMCs),i.e. programmable hardware modules, within a real-time embeddedelectronic system. The ECS uses the workload estimations to setPerformance-Power (PP) settings (or states) of the PMCs dynamically tolevels high enough to deliver instantaneous performance needed toprocess the workload in time to meet real-time deadlines, but no higherthan necessary, thereby minimising power wastage.

It therefore follows, in relation to the processor, that the PP states,for example operating clock frequency and operating voltage, of theprocessor ideally should be set just high enough to ensure thatapplication programs and other critical software execute fast enough tomeet real-time processing deadlines, but not higher than necessary,thereby avoiding wastage of power. Time leading up to the real-timedeadline not required for workload processing constitutes so-calledslack-time during which energy-saving measures, through setting of thePP states, can potentially be invoked. Further, for optimal energyconservation the PP states should be set in real-time as the workload,for example a software program, is being processed.

Unfortunately, there are penalties or ‘costs’ in both power consumptionand time in transitioning between PP states of a given piece ofhardware. These costs can easily outweigh the (energy-saving) benefitsof the PP state to be used and so for optimal energy conservation somecost-benefit analysis should be performed in real-time to qualify adecision as to whether or not (and when) to make a particular transitionto a potentially energy-saving PP state. Such cost-benefit analysis isdescribed for various PP mechanisms, such as shutdown or idle modes, inpublic domain literature, for example: “A Survey of Design Techniquesfor System-Level Dynamic Power Management” (L. Benini, A. Bogliolo, G.De Micheli, IEEE Transactions On Very Large Scale Integration (VLSI)Systems, Vol. 8, No. 3, June 2000), “Energy-Conscious, Deterministic I/ODevice Scheduling in Hard Real-Time Systems” (V. Swaminathan, K.Chakrabarty, IEEE Transactions On Computer-Aided Design Of IntegratedCircuits And Systems, Vol. 22, No. 7, July 2003), or “Improving EnergySaving in Wireless Systems by Using Dynamic Power Management” (C.Chiasserini, R. R. Rao, IEEE Transactions On Wireless Communications,Vol. 2, No. 5, September 2003). However, in some energy conservationimplementations no cost-benefit analysis is performed. Further, whenpresent, the cost-benefit qualification is specific to a particularpower-saving design employed by, and the fabrication characteristics of,the PP mechanism, i.e. a hardware-specific ad-hoc solution is employedthat makes the ECS complex, hard to maintain and difficult to port tonew hardware platforms.

STATEMENT OF INVENTION

According to the present invention, there is provided an electronicapparatus and a method of conserving energy as set forth in the appendedclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

At least one embodiment of the invention will now be described, by wayof example only, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of an electronic apparatus of FIG. 1;

FIG. 2 is a schematic diagram of an energy-conserving module interfacingwith hardware of FIG. 1;

FIG. 3 is a schematic diagram of platform cost rules used by theenergy-conserving module of FIG. 2;

FIG. 4 is a flow diagram of an initialisation part of a method ofconserving energy employed by the energy-conserving module of FIG. 2;and

FIG. 5 is a flow diagram of a run-time part of the method of conservingenergy employed by the energy-conserving module of FIG. 2.

DESCRIPTION OF PREFERRED EMBODIMENTS

Throughout the following description identical reference numerals willbe used to identify like parts.

Referring to FIG. 1, a portable computing device, for example aso-called smartphone 100 constitutes a combination of a computer and atelecommunications handset. Consequently, the smartphone 100 comprises aprocessing resource, for example a processor 102 coupled to one or moreinput device 104, such as a keypad and/or a touch-screen input device.The processor 102 is also coupled to a volatile storage device, forexample a Random Access Memory (RAM) 106, and a non-volatile storagedevice, for example a Read Only Memory (ROM) 108.

A data bus 110 is also provided and coupled to the processor 102, thedata bus 110 also being coupled to a video processor 112, an imageprocessor 114, an audio processor 116 a plug-in storage module, such asa flash memory storage unit 118, and a power management unit 119.

A digital camera unit 115 is coupled to the image processor 114, and aloudspeaker 120 and a microphone 121 are coupled to the audio processor116. An off-chip device, in this example a Liquid Crystal Display (LCD)panel 122, is coupled to the video processor 112.

In order to support wireless communications services, for example acellular telecommunications service, such as a Universal MobileTelecommunications System (UMTS) service, a Radio Frequency (RF) chipset124 is coupled to the processor 102, the RF chipset 124 also beingcoupled to an antenna 126.

The above-described hardware constitutes a hardware platform and theskilled person will understand that one or more of the processor 102,the RAM 106, the video processor 112, the image processor 114 and/or theaudio processor 116 can be manufactured as one or more IntegratedCircuit (IC), for example an application processor or a basebandprocessor (not shown).

Each of the processor 102, the RAM 106, the video processor 112, theimage processor 114 and the audio processor 116 constitutes a PowerManaged Component (PMC). Each of the PMCs comprises at least one powersaving mechanisms (not shown) that is used in this example, by softwarein order to minimise power usage by the PMCs whilst maintaining aminimum level of performance required of each PMC to process, store,transfer, or otherwise manage, data within real-time output constraintsor remain substantially inactive. Examples of power saving mechanismsinclude Dynamic Voltage Scaling, Dynamic Frequency Scaling, and/or oneor more low-power idle modes.

Whilst the above example of the portable computing device has beendescribed in the context of the smartphone 100, the skilled person willappreciate that other portable computing devices can constitute theportable computing device. Further, for the sake of the conciseness andclarity of description, only parts of the smartphone 100 necessary forunderstanding the embodiments herein are described; the skilled personwill, however, appreciate that other technical details are associatedwith the smartphone 100.

Turning to FIG. 2, an energy-conserving module 200 is supported by andworks closely with an operating system, for example Linux, running onthe processor 102. The energy-conserving module 200 comprises aperformance estimation module 202 capable of communicating with acost-benefit qualifier module 204. The cost-benefit qualifier module 204implements, when in use, one or more cost-benefit algorithms 206, and isalso capable of communicating with a performance-setting module 207. Theperformance-setting module 207 is, in turn, capable of communicatingwith the PMCs 102, 106, 112, 114, 116 of the hardware platform in orderto transition one or more of the PMCs 102, 106, 112, 114, 116, betweenrespective two or more Performance-Power (PP) states.

In addition to supporting the energy-conserving module 200, a pluralityof Platform Cost Rules (PCRs) 210 specific to the hardware platformresides with the energy-conserving module 200. The nature of the PCRs210 will be described in greater detail later herein.

In this example, each PCR is an array of nine fields (FIG. 3). A firstfield 300 is reserved to identify a Performance-Power (PP) mechanismtype, for example a low-power idle mode mechanism, a dynamic frequencyscaling mechanism or a dynamic voltage scaling mechanism. A second field302 is reserved to identify a PMC to which the PCR refers, for example amicroprocessor core. A third field 304 is reserved to identify a mode ofoperation of the PP mechanism type identified in the first field 300,for example a sleep mode or a doze mode. A fourth, fifth, sixth,seventh, eighth and ninth field 306, 308, 310, 312, 314, 316 constitutea fixed list of parametric arguments that characterise the PP mechanismand constitute a so-called Power State Model (PSM).

In the present example, parameters of the Power State Model (PSM) are: apower in an Active state (P_(a)), a power in an Inactive state (P_(i)),a power used to transition from the Active state to the Inactive state(P_(ai)), a power used to transition from the Inactive state to theActive state (P_(ia)), a time to transition from the Active state to theInactive state (T_(ai)), and a time to transition from the Inactivestate to the Active state (T_(ia)).

However, the generality of the PCRs is such that the skilled person willappreciate that a given PCR can comprise any number and type ofparameters to support one or more PP mechanism, such as the DynamicVoltage Scaling (DVS) mechanism and the Dynamic Frequency Scaling (DFS)mechanism. Further, a number of PCRs can be provided to support other PPmechanisms for one or more devices. In such circumstances, a PCR can beprovided to characterise each discrete frequency and/or voltage level ofthe DFS and/or DVS mechanism and the parameters to define the PSM canvary in significance and number of fields. Since a wide variety ofdevices exist and new types of PP mechanism can be devised as well asexisting PP mechanisms improved, the skilled person will also appreciatethat the use of PCRs is flexible and not limited to a fixed list of PPmechanisms and/or devices. For example, the parametric arguments candefine a set of operating points or a mathematical function thatdescribes one or more relationship between power and performance of agiven PP mechanism. It can therefore be seen that the one or morecost-benefit algorithm 206 is generic, but configurable using one ormore PCR.

In operation (FIG. 4), a given software application, for example, astreamed video application is supported by the processor 102. Thestreamed video application is instructed, through user interaction, toreceive and process real-time streamed video data. The streamed videodata is, in this example, obtained from a cellular communicationsnetwork with which the smartphone 100 is connected using the RF chipset124 of the smartphone 100. However, the skilled person will appreciatethat the video data can be obtained through other means, for example, alocally-stored video file.

The received data is organised as frames of video data resulting in thevideo application processing each frame of data sequentially. Processingof one or more frame of data or inactivity when not processing the oneor more frame of data constitutes, herein, a processing function. Inorder to process a given frame of data, the performance estimationmodule 202 of the energy-conserving module 200 employs known PPestimation techniques, for example, a process utilisation historyalgorithm to determine (Step 400) a level of performance required toprocess the given frame of data.

In an Active state (run mode), the processor 102 processes the videodata. After processing a first frame of video data, an idle time canexist until the processor 102 has to process a subsequent frame of thevideo data.

Consequently in this example, the processor 102 has an idle mode intowhich the processor 102 can enter in order to make use of the idle timeto conserve energy, a PCR 318 accessible by the energy-conserving module200 comprising power characteristics of the idle mode with respect tothe run mode of the processor 102.

In this example the parameters of the idle mode of the processor 102 arefixed because the parameters relate to the hardware designcharacteristics of the processor 102. Hence, referring to FIG. 4, thePCR 318 can be retrieved (Step 400) by the energy-conserving module 200at start-up of the smartphone 100 and the parameters of the PCR 318extracted (Step 402) (reproduced in Table I below) and used by one (ormore) of the cost-benefit algorithms 206, for example to calculate (Step404) a break-even time constituting a second duration, T_(be).

TABLE I POWER STATE MODEL (PSM) PARAMETERS Normalised Parameter ValueUnit Description Values Units P_(a) 100 mW Power in Active 0.1 W state(run mode) P_(i) 20 mW Power in Inactive 0.02 W state (Sleep mode)P_(ai) 90 mW Power to transition 0.09 W from Active to Inactive stateP_(ia) 120 mW Power to transition 0.12 W from Inactive to Active stateT_(ai) 50 μsec Time to transition 0.00005 S from Active to Inactivestate T_(ia) 100 μsec Time to transition 0.0001 s from Inactive toActive state

In this example, the one of the cost-benefit algorithms 206 implementsthe following equation:

$T_{be} = {{T_{ai}\frac{\left( {P_{ai} - P_{i}} \right)}{\left( {P_{a} - P_{i}} \right)}} + {T_{ia}\frac{\left( {P_{ia} - P_{i}} \right)}{\left( {P_{a} - P_{i}} \right)}}}$where: T_(be) is a break-even duration;

-   -   T_(ai) is a time taken to transition from the Active state (run        mode) to the Inactive state (Sleep mode);    -   T_(ia) is a time taken to transition from the Inactive state to        the Active state;    -   P_(ai) is a power used to transition from the Active state to        the Inactive state;    -   P_(ia) is a power used to transition from the Inactive state to        the Active state;    -   P_(a) is a power used by the processor 102 when in the Active        state; and    -   P_(i) is a power used by the processor 102 when in the Inactive        state.

Evaluation of the above equation is shown in Table II below:

TABLE II Calculated Variable Units Significance Values E_(a) J Energythat would be used 0.000020 J during the slack time, T_(i), if the PMCremains in the Active state E_(i) J Energy that would be used 0.000018 Jduring the slack time, T_(i), if the PMC enters into the Inactive stateE_(s) J Energy Saved or Wasted by 0.000003 J entering the Inactive state(E_(a) − E_(i)) T_(be) Sec Duration of PMC in the 0.00017 sec Inactivestate needed to consume the same amount of energy as if the PMC hadremained in the Active state (the break-even time), i.e. T_(i) = T_(be)when E_(a) = E_(i)

Referring to FIG. 5, the performance estimation module 202 periodicallyestimates (Step 500), in accordance with the PP estimation techniqueimplemented by the performance estimation module 202, a level ofperformance required of the processor 102 by the video application usingany suitable known estimation technique. Additionally, a first duration,constituting a period of time during which workload processing is notrequired of the processor 102, is calculated (Step 502). In the case ofthe idle time between processing of the frames described above, theperformance estimation module 202 provides to the cost-benefit qualifiermodule 204 the level of performance required and a so-called slack time,T_(i), corresponding to the first duration. The slack time is, in thisexample, a potential idle time for the processor 102 and is determinedby the performance estimation module 202 to be 200 μs. The cost-benefitqualifier module 204 then invokes (Step 504), if required, one or moreof the cost-benefit algorithms 206 in order to evaluate parametersrecorded as the PCR 318. In the present example, the PCR 318 onlycomprises parameters that, as mentioned above, are set during design ofthe processor 102 and so has already been evaluated by the calculationof the break-even time, T_(be). However, in some embodiments PCRs can beused by one or more cost-benefit algorithm 206 that also requires one ormore parameter only obtainable during run-time of the processor 102.

The cost-benefit qualifier module 204 then determines (Step 506) whetherthe slack time, T_(i), is greater than the break-even time, T_(be). Ifthe slack time is not greater than the break-even time, T_(be), thecost-benefit qualifier module 204 instructs (Step 508) theperformance-setting module 207 to keep the processor 102 in the run modeand takes no further action until a new estimated performance level iscommunicated from the performance estimation module 202 to thecost-benefit qualifier module 204.

Hence, as can be seen from Table II above for this example, the slacktime, T_(i), (200 μs) is greater than the break-even time, T_(be), ofapproximately 168.75 μs. Therefore, if the processor 102 were to enterinto and remain in the sleep mode, continuance of the processor 102 inthe sleep mode after 168.75 μs would result in a net energy saving.Consequently, the cost-benefit qualifier module 204 sets (Step 510) theprocessor 102 to enter the sleep mode at a beginning of the slack time.

In another example, a new slack time, T_(i)=50 μs, as calculated by theperformance estimation module 202 during a subsequent performanceestimation cycle is only 50 μs. However, the parameters of the processor102 remain unchanged and so the energy-consumption statistics associatedwith the processor 102 also remain unchanged as shown in Table IIIbelow. Since the break-even time remains at 168.75 μs, i.e. greater thanthe new slack time, transition of the processor 102 into the sleep modefor only 50 μs would result in a net loss of energy as compared toenergy consumed by maintaining the processor 102 in the current, run,mode. Consequently, the cost-benefit qualifier module 204 does not setthe processor 102 to enter into the sleep mode.

Whilst the above examples have been described in the context of theprocessor 102 only having the sleep mode, the skilled person willappreciate that the above-described hardware and/or modules can be usedto control other energy-saving mechanisms, for example an idle mechanismhaving two or more modes. Similarly, the hardware, for example theprocessor 102, can have multiple energy-conserving mechanisms for theActive state, each energy-conserving mechanism optionally having one ormore respective PP state.

In such embodiments, a PCR is provided for each mode of the mechanismand the plurality of PCRs is processed by one or more cost-benefitalgorithm 206. Where more than one cost-benefit algorithm 206 isevaluated resulting in a number of energy-saving candidate modes thatcan be set for the processor 102 (or other PMC), an optimumenergy-saving mode is selected.

Alternative embodiments of the invention can be implemented as acomputer program product for use with a computer system, the computerprogram product being, for example, a series of computer instructionsstored on a tangible data recording medium, such as a diskette, CD-ROM,ROM, or fixed disk, or embodied in a computer data signal, the signalbeing transmitted over a tangible medium or a wireless medium, forexample, microwave or infrared. The series of computer instructions canconstitute all or part of the functionality described above, and canalso be stored in any memory device, volatile or non-volatile, such assemiconductor, magnetic, optical or other memory device.

It is thus possible to provide an electronic apparatus and method ofconserving energy that ensures that a benefit of switching PP states isnot outweighed by any energy use costs involved in making such atransition. Hence, optimal time to switch PP states is determined. Wherea PMC has two or more energy-saving mechanisms, it is possible todetermine, “on the fly” which of the various energy-saving mechanisms touse in preference to other energy-saving mechanisms available in orderto achieve optimal overall energy conservation. Further, the method andapparatus is not dependent upon characteristics of the design of thePMCs and/or silicon process used to fabricate the PMCs. Consequently,the apparatus and method perform real-time analysis whilst remaininghighly portable across many hardware platforms. The apparatus istherefore less complex and cheaper to produce. Additionally, the methodand apparatus benefit from ease of implementation, maintenance andenhancement. Of course, the above advantages are exemplary, and these orother advantages may be achieved by the invention. Further, the skilledperson will appreciate that not all advantages stated above arenecessarily achieved by embodiments described herein.

1. An electronic apparatus comprising: a hardware element arranged tooperate in a first energy usage mode for providing a first level ofperformance, the hardware element having a second energy usage mode forproviding a second level of performance; an energy-conservation modulearranged to determine a performance level required of the hardwareelement based on a platform cost rule for the hardware element and afirst duration for providing the performance level, wherein the platformcost rule includes a plurality of fields identifying parameters for thehardware element including a first field identifying that a powermechanism associated with the hardware element uses dynamic frequencyscaling or dynamic voltage scaling; and a store comprising dataassociated with the hardware element transitioning between the firstenergy usage mode and the second energy usage mode, the datacharacterising power use and performance; wherein the energyconservation module is arranged to use the data to determine whether anenergy saving is achievable should the hardware element transition intothe second energy usage mode and use the second energy usage mode inorder to satisfy the performance level required during the firstduration.
 2. An apparatus as claimed in claim 1, wherein the performancelevel required is lower than the first level of performance.
 3. Anapparatus as claimed in claim 1, wherein the energy-conservation moduleis arranged to determine a break-even energy in relation to use of thesecond energy usage mode for providing the second level of performance.4. An apparatus as claimed in claim 3, wherein the break-even energycorresponds to a second duration that, when exceeded, results in theenergy saving.
 5. An apparatus as claimed in claim 1, wherein theenergy-conservation module is arranged to permit use of the secondenergy usage mode in response to the energy-conservation moduledetermining that use of the second energy usage mode results in theenergy saving.
 6. An apparatus as claimed in claim 4, wherein theenergy-conservation module is arranged to permit use of the secondenergy usage mode in response to the first duration exceeding the secondduration.
 7. An apparatus as claimed in claim 1, wherein theenergy-conservation module is arranged to determine whether use of thesecond energy usage mode results in the energy saving using a first atleast one parameter relating to transitioning into the second energyusage mode.
 8. An apparatus as claimed in claim 1, wherein theenergy-conservation module is arranged to determine whether use of thesecond energy usage mode results in the energy saving using a second atleast one parameter relating to transitioning out of the second energyusage mode.
 9. An apparatus as claimed in claim 7, wherein the first atleast one parameter is selected from at least one of: a time totransition into the second energy usage mode; a power used to transitioninto the second energy usage mode; power used by the hardware elementwhen in the second energy usage mode; and/or power used by the hardwareelement when in the first energy usage mode.
 10. An apparatus as claimedin claim 8, wherein the second at least one parameter is selected fromat least one of: a time to transition out of the second energy usagemode; power used to transition out of the second energy usage mode;power used by the hardware element in the second energy usage mode;and/or power used by the hardware element when in the first energy usagemode.
 11. An apparatus as claimed in claim 9, wherein the energyconservation module employs a following formula to determine whether useof the second energy usage mode results in the energy saving:$T_{be} = {{T_{ai}\frac{\left( {P_{ai} - P_{i}} \right)}{\left( {P_{a} - P_{i}} \right)}} + {T_{ia}\frac{\left( {P_{ia} - P_{i}} \right)}{\left( {P_{a} - P_{i}} \right)}}}$where: T_(be) is an energy break-even interval; T_(ai) is the time takento enter into the second energy usage mode; T_(ia) is a time taken toleave the second energy usage mode; P_(ai) is the power used to enterinto the second energy usage mode; P_(ia) is a power used to leave thesecond energy usage mode; P_(a) is the power used by the hardwareelement when in the first energy usage mode; and P_(i) is the power usedby the hardware element when in the second energy usage mode.
 12. Anapparatus as claimed in claim 1, wherein the first and second energyusage modes are provided by a same energy-saving mechanism supported bythe hardware element.
 13. An apparatus as claimed in claim 1, whereinthe first energy usage mode is provided by a first energy-savingmechanism supported by the hardware element and the second energy usagemode is provided by a second energy-saving mechanism supported by thehardware element.
 14. An apparatus as claimed in claim 12, wherein thesame energy-saving mechanism is scalable.
 15. An apparatus as claimed inclaim 1, wherein the energy-conservation module implements at least onegeneric algorithm and uses the data in conjunction with the at least onegeneric algorithm to determine whether use of the second energy usagemode results in the energy saving, the at least one generic algorithmrelating to a hardware implementation comprising the hardware element.16. An apparatus as claimed in claim 15, wherein the at least one of theat least one generic algorithm is arranged to apply the data todetermine whether use of the second energy usage mode results in theenergy saving.
 17. An apparatus as claimed in claim 1, wherein the datais loadable by the energy-conservation module.
 18. A method ofconserving energy used by a hardware element in an electronic apparatus,the method comprising the steps of: providing the hardware element witha first energy usage mode for providing a first level of performance,and a second energy usage mode for providing a second level ofperformance; determining a performance level required of the hardwareelement based on a platform cost rule for the hardware element and afirst duration for providing the performance level, wherein the platformcost rule includes a plurality of fields identifying parameters for thehardware element including a first field identifying that a powermechanism associated with the hardware element uses dynamic frequencyscaling or dynamic voltage scaling; and providing data associated withthe hardware element transitioning between the first energy usage modeand the second energy usage mode, the data characterising power use andperformance; wherein using the data to determine whether an energysaving is achievable should the hardware element transition into thesecond energy usage mode and use the second energy usage mode in orderto satisfy the performance level required during the first duration. 19.A non-transitory computer readable medium including computer code whoseexecution causes a computer to perform the steps comprising: providingthe hardware element with a first energy usage mode for providing afirst level of performance and a second energy usage mode for providinga second level of performance; determining a performance level requiredof the hardware element based on a platform cost rule for the hardwareelement and a first duration for providing the performance level,wherein the platform cost rule includes a plurality of fieldsidentifying parameters for the hardware element including a first fieldidentifying that a power mechanism associated with the hardware elementuses dynamic frequency scaling or dynamic voltage scaling; and providingdata associated with the hardware element transitioning between thefirst energy usage mode and the second energy usage mode, the datacharacterising power use and performance; wherein using the data todetermine whether an energy saving is achievable should the hardwareelement transition into the second energy usage mode and use the secondenergy usage mode in order to satisfy the performance level requiredduring the first duration.
 20. An apparatus as claimed in claim 1,wherein the plurality of fields identifying parameters for the hardwareelement further includes a second field identifying the hardware elementassociated with the platform cost rule, a third field identifying a modeof operation for the power mechanism, and additional fields identifyinga list of parametric arguments that constitute a power state model.